The present invention relates to cache memory in a system having first and second level caches, and in particular relates to the storing of tag address and status information for the cache.
Many computer systems today use multiple cache memories to speed up retrieval of data. Such a system will typically have an array of DRAM chips for the main memory. The microprocessor chip itself can have a small, on-chip cache memory which is quickly accessed. This is referred to as a first level (L1) cache. In addition, a second level cache (L2), which is bigger than the microprocessor on-chip cache, is also used. This is typically a cache memory of SRAM chips, which are faster than the DRAM chips, but also more expensive than the DRAMs.
Both cache memories will contain a subset of what is in main memory. The first level cache will be a subset of what is in the second level cache. In operation, the microprocessor will first look in the first level cache, and then the second level cache before going to main memory. To maintain consistency in the caches, when data is written into the first level cache, the corresponding entry in the second level cache and eventually main memory needs to be updated as well. It is desirable to optimize the timing for these updates.
Since the cache is smaller than main memory, multiple main memory locations may be mapped into the same cache location. The cache entries must contain not only the relevant data, but also enough information ("tag address and status" bits) about the address associated with the data to be unambiguous. Hence, the cache must be wider than the data stored in it. To improve the cache "hit ratio", it is also desirable for the caches to be set associative, i.e., a particular location in memory may be stored in multiple locations ("sets") in the cache. The width of the cache (and the number of SRAMs used to implement the cache) doubles or quadruples for a 2- or 4-way set associative cache, respectively, compared to a 1-way set associative ("direct mapped") cache. It is desirable to reduce the number of SRAMs required to implement a cache from both cost and electrical performance reasons.